a) Write a finite state machine (FSM) for an automatic reversible 6 modulo counter as follows: The counter counts 0, 1, 2, 3, 4, 5 (when its internal memory input is registering 0) and reverses: 5 4, 3, 2, 1, 0 (when its internal memory input is registering 1) b) As a result of a) above, design and implement a minimal logic circuit for the automatic reversible 6 modulo counter. If the counter were to enter any of the unwanted states, it should be reset to count from 0 on the next clock pulse. Hint: The counter uses 4 bits. Let the most significant bit (MSB) be the memory bit that the counter will set as 0 for counting up and will reset it to 1 when counting downwards.